1. Related Application and Priority Information
This application claims priority to and the benefit of Korean Patent Application No. 10-2005-62313 filed in the Korean Intellectual Property Office on Jul. 11, 2005, the entire contents of which are incorporated herein by reference.
2. Field of the Invention
The present invention relates to a nonvolatile memory technologies, and more specifically, to a method for manufacturing NOR flash memory devices.
3. Description of the Related Art
Semiconductor memory devices can be divided into RAM (Random Access Memory) and ROM (Read Only Memory), and the ROM devices are classified into mask ROMs and programmable ROMs (PROM). With the mask ROM, data is written or recorded when the memory is manufactured, while data in PROM can be altered by users. The PROM includes erasable PROMs (EPROMs), which allow the user to erase the data stored in the memory device by using ultraviolet source and then program it, electrically erasable PROMs (EEPROMs) that can be programmed and erased electrically, and flash memories that allow multiple memory locations to be erased or written in one programming operation.
Flash memory has a stacked gate structure comprising a floating gate and a control gate. The floating gate, placed between the control gate and the semiconductor substrate, is isolated by an insulating oxide layer. When electrons are on the floating gate, they modify the electric field coming from the control gate, which modifies the threshold voltage of the cell. Thus, when the flash memory cell is “read” by applying a specific voltage to the control gate, electrical current will either flow or not flow, depending on the threshold voltage of the cell, which is controlled by the electrons on the floating gate. This presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data. The flash memory device may be made in two forms: NOR flash and NAND flash. The NOR flash memory cells are connected in parallel between bit lines and grounds, and have common source by which sixteen cells have one common contact point and the sixteen source lines are interconnected by n+ diffusion layer.
Recently, shallow trench isolation (STI) and self-aligned source (SAS) technologies have been employed for high integration of the flash memory devices, especially for reducing the cell size along both the word line and bit line directions.
FIG. 1 shows the structure of conventional NOR flash memory device to which the STI and SAS technologies have been applied. The memory cell has drain (D) and source (S) disposed at both sides of the common word line (WL), and each of the memory cells is electrically separated by an insulating layer formed in a trench of the isolation region (ISO). The sources of the memory cells are interconnected by the SAS process.
More specifically, the SAS process is carried out after forming a gate stack consisting of a tunnel oxide layer 12, a floating gate 13, a dielectric layer 14 and a control gate 15 as shown in FIGS. 3A and 3B. In the SAS process, sources of eight to sixteen bit cells are opened at the same time and the insulating layer of the ISO is removed. Thus, in the common source region, a trench 20 is formed within the substrate 10 as shown in FIG. 2. In this formed common source region, an ion implantation layer 30 is formed by ion-implanting dopants (As or P) into the substrate. The ion implantation layer 30 forms a common source line to electrically interconnect the sources of the memory cells.
According to the conventional SAS processes, the gate stack consisting of floating gate 13, dielectric layer 14 and control gate 15 experiences a profile variation during the removal of the insulating layer in the ISO, which is performed with the use of photoresist pattern for opening the common source region as a mask. In other words, as shown in FIG. 3A, the gate stack has vertical profile along cross section (A) toward the common source region before the SAS process. However, when the SAS process is performed, parts of control gate 15, dielectric layer 14, and floating gate 13 are damaged, and as shown in FIG. 3B, the gate stack has an inclined profile along the cross section. In FIG. 3B, ‘PR’ represents a mask pattern used in an ion implantation process.
With the inclined profile of the gate stack, the floating gate 13, dielectric layer 14 and control gate 15 may be harmed during the subsequent ion implantation process for forming the common source line. Particularly, part of dielectric layer 14 is exposed due to the inclined profile as shown in FIG. 3B, which results in dopants injection into the exposed part (B), and the dielectric capacity between the floating gate 13 and control gate 15 may be degraded. As a result, the coupling ratio is decreased and the performance of memory device may be compromised.
Moreover, the flash memory has an ability to store electrons for a long time in the gate stack consisting of floating gate, dielectric layer and control gate, and thus the damage to the gate stack has to be avoided if at all possible. With a damaged gate stack, it is not possible to guarantee the intended lifespan of the flash memory devices.